By Topic

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Kuriyama, H. ; ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Ashida, M. ; Tsutsumi, K. ; Maegawa, S.
more authors

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-μm design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT

Published in:

Electron Devices, IEEE Transactions on  (Volume:46 ,  Issue: 5 )