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A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

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4 Author(s)
Farjad-Rad, R. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Yang, C.-K.K. ; Horowitz, M.A. ; Lee, T.H.

A serial link transmitter fabricated in a large-scale integrated 0.4-μm CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5×2.0 mm2 of die area

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 5 )

Date of Publication:

May 1999

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