Cell-Plate Line Connecting Complementary Bitline (c/sup 3/) Architecture For Battery Operating DRAMs

With high density DRAMs, low voltage operation is of great concern. The most important point here is having a sufficiently high signal-to-noise ratio. This paper describes an approach from circuit design, which is called Cell-plate line Connecting Complementary bitline (C3) architecture. It achieves a high signal-to-noise ration and high reliability without adding to the process steps or increasing the memory cell area. A read out voltage difference of 130mV at 1.5V power supply is obtained by the test device having a cell size of 1.6x3.2μm2 and using the 16Mb DRAM process [1].