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Formal verification method for combinatorial circuits at high level design

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3 Author(s)
Kitamichi, J. ; Graduate Sch. of Eng. Sci., Osaka Univ., Japan ; Kageyama, H. ; Funabikiy, N.

In this paper, we propose a formal verification method for combinatorial circuits at high level design. The specification is described by both integer and Boolean variables for input and output variables, and the implementation is described by only Boolean variables. Our verification method judges the equivalence between the specification and the implementation by deciding the truth of the Presburger sentence. We show experimental results on some benchmarks, such as a 4 bit ALU and multiplier, by our method

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999

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