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A scalable pipelined architecture for separable 2-D discrete wavelet transform

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4 Author(s)
Jer Min Jou ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Pei-Yin Chen ; Yeu-Horng Shiau ; Ming-Shiang Liang

This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for the computation of 2-D DWT. With these properties, it is easily scalable for different filter lengths and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999