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Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

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3 Author(s)
Dhanwada, N.R. ; Lab. for Digital Design Environ., Cincinnati Univ., OH, USA ; Nunez-Aldana, A. ; Vemuri, R.

In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher level on analog circuit synthesis are presented demonstrating the effectiveness of this technique

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999