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An efficient approach to constrained via minimization for two-layer VLSI routing

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3 Author(s)
Tang, M. ; Centre for Very High Speed Microelectron. Syst., Edith Cowan Univ., Perth, WA, Australia ; Eshraghian, K. ; Hon Nin Cheung

Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999

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