Referenced Items are not available for this document.
Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate
Published in:
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Date of Conference: 18-21 Jan 1999
- Page(s):
- 149 - 152 vol.1
- Meeting Date :
- 18 Jan 1999-21 Jan 1999
- Print ISBN:
- 0-7803-5012-X
- INSPEC Accession Number:
- 6358272
- Conference Location :
- Wanchai
- Digital Object Identifier :
- 10.1109/ASPDAC.1999.759982
- Product Type:
- Conference Publications
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