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A new single-clock flip-flop for half-swing clocking

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4 Author(s)
Young-Su Kwon ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Bong-Il Park ; In-Cheol Park ; Chong-Min Kyung

We propose a new flip-flop configuration which saves about 60% of total clocking power using a half-swing clock. To use the half-swing clock, level converters or special clock drivers are traditionally required and the power consumptions of this logic cannot be ignored. In the proposed scheme, only NMOS devices are clocked with a half-swing clock in order to make it operate without the level converter or any other additional logics, and the random logic circuits except for the clock and flip-flops are supplied by Vcc while the clock network is supplied by Vcc/2. Compared to the conventional scheme, a great amount of power consumed in clocking which is responsible for a large portion of total chip power can be saved with the proposed new flip-flop configuration

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999