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An LSI implementation of an adaptive genetic algorithm with on-the-fly crossover operator selection

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6 Author(s)
S. Wakabayashi ; Fac. of Eng., Hiroshima Univ., Japan ; T. Koide ; N. Toshine ; M. Goto
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This paper describes an LSI implementation of a genetic algorithm (GA), called the Genetic Algorithm Accelerator (GAA) chip. The GAA chip is an LSI implementation of a GA, in which two types of crossover operators are supported, and the operator to be actually used in the algorithm is not fixed in advance, but dynamically selected for each pair of chromosomes in the algorithm execution. The GAA chip has been designed with the Verilog HDL and simulated with some benchmark functions. According to the simulation, the GAA chip will run with a maximum 50 MHz clock. The chip has been fabricated with CMOS 0.5 μm standard cell technology

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999