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A 10 b 58 MHz CMOS A/D converter for high-speed video applications

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4 Author(s)
Byeong-Lyeol Jeon ; Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea ; Kang-Jin Lee ; Seung-Hoon Lee ; Sang-Won Yoon

This paper describes a 10 b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 μm CMOS show less than ±0.6 LSB and ±2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz

Published in:

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Date of Conference:

18-21 Jan 1999