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A parallel embedded-processor architecture for ATM reassembly

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2 Author(s)
Hobson, R.F. ; Sch. of Comput. & Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada ; Wong, P.S.

The asynchronous transfer mode (ATM) reassembly algorithm for adaptation layer five is broken down into concurrent tasks for efficient VLSI implementation. VHDL and HSPICE simulations show that the proposed reassembly chip architecture will function with ATM line rates up to 700 Mb/s. The architecture is based upon three embedded lightweight processors, a variety of supporting circuitry, and a peripheral component interface (PCI) bus host interface. An important architectural feature is the use of a paged memory management system for the reconstruction of variable length messages

Published in:

Networking, IEEE/ACM Transactions on  (Volume:7 ,  Issue: 1 )

Date of Publication:

Feb 1999

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