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In CMOS ICs, reducing V/sub DD/ reduces dynamic power quadratically since P/sub dynamic/=/spl alpha/C/sub L/V/sub DD/V/sub swing/f. However, without a corresponding decrease in the threshold voltage V/sub TH/, the delay increases rapidly particularly for large C/sub L/. Decreasing V/sub TH/, on the other hand, leads to large leakage currents. Another method to decrease P/sub dynamic/ without sacrificing delay is to decrease V/sub swing/. A charge sharing model, HiCapCS, is used to reduce V/sub swing/ on heavily-loaded lines in dynamic CMOS circuits.
Date of Conference: 17-17 Feb. 1999