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A block diagram of the three-port register file is shown. The memory cell for this register file is also shown. A bit line driver, implemented using a differential ECL buffer, sets the differential voltage across WE and WBb according to the value to be written. During a write, current is drawn through WW, while no current is drawn through WWb. This forces the differential voltage between MC and MCb to equal the voltage between WE and WBb. When the current is shifted from WW to WWb after the write is finished, the positive feedback of device QF and QFb maintains the differential voltage across MC and MCb. When the memory cell is selected during a read on read port A, current is drawn through RAW. This forces current to flow through either RAB or RABb, depending on whether MC or MCb has a higher voltage level. The sense amplifier determines through which bit line current is flowing. Read port B operates under the same principle. A diode connected between VCC and TW is used to bias the memory cells in each row compatibly with sense amplifier biasing.