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An I/O transceiver for scalable multiprocessor systems with 1.25 Gb/s parallel bandwidth and 7.7 ns latency performs as a plesiochronous link and compensates for skin-effect cable loss and inter-wiring skew across 20 m cable connections. Phase-interpolator-based clock recovery integrates multiple I/O links that can tolerate slight differences in frequencies between incoming and internal reference clocks. A differential partial-response detection (DPRD) receiver ensures low latency equalization for skin-effect cable loss of up to 10 dB. The receivers are equipped with deskew circuitry to tolerate up to 6.4 ns inter-wiring skew for 20 data bits. The data rate, driver output level, and receiver clock phase are adjusted automatically by a logic sequencer, basic control, which maximizes data rate and minimizes power consumption without external manual adjustment, adapting from onboard PCB traces to 20 m twisted-pair cables.
Date of Conference: 17-17 Feb. 1999