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A 256 Mb multilevel flash memory with 2 MB/s program rate for mass storage applications

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18 Author(s)
A. Nozoe ; Hitachi Ltd., Tokyo, Japan ; H. Kotani ; T. Tsujikawa ; K. Yoshida
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A 256 Mb flash memory in 0.26 /spl mu/m CMOS on a 138.6 mm/sup 2/ die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation.

Published in:

Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International

Date of Conference:

17-17 Feb. 1999