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Recent attempts to reduce the cost and size of wireless transceivers feature higher levels of transistor integration in alternative architectures to reduce the need for the off-chip, high-Q passives used in present-day super-heterodyne transceivers. Unfortunately, removal of off-chip passives often comes at the cost of increased power consumption in circuits preceding and including the analog-to-digital converter (ADC), which must have higher dynamic ranges to avoid desensitization caused by larger adjacent channel interferers. A selectivity (Q) versus power trade-off is seen here. This device makes possible a paradigm-shifting transceiver architecture that, rather than eliminate high-and passive components, attempts to maximize their role with the intention of harnessing the above Q versus power trade-off.