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Resynthesis and retiming for optimum partial scan

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2 Author(s)
S. T. Chakradhar ; NEC Res. Inst., Princeton, NJ, USA ; S. Dey

An effective partial scan approach selects flip-flops (FPs) in the minimum feedback vertex set (MFVS) of the FF dependency graph, so that all loops, except self-loops, are broken. However, the MFVS of the circuit (the minimum number of gates whose removal makes the circuit acyclic) is a lower bound and in many cases, significantly smaller than the MFVS of the FF dependency graph. Since only FFs can be considered for scan, this paper investigates the possibility of repositioning FFs so that, in the modified circuit, every circuit MFVS gate drives at least one FF that can be scanned. We show that resynthesis and retiming can always transform any circuit into an equivalent circuit whose FF dependency graph MFVS is equal to the MFVS of the original circuit. Therefore, the MVFS of a circuit is a tight lower bound on the number of scan FFs needed. We first identify the necessary and sufficient conditions under which legal retiming can produce the desired FF repositioning. We show that circuits that do not satisfy these conditions can always be suitably modified using two new resynthesis transformations. The modified circuit can always be retimed to achieve the desired FF repositioning. Experimental results for several large sequential benchmarks show that the number of scan FFs required for the resynthesized and retimed circuit is significantly smaller than that required for the original circuit

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:18 ,  Issue: 5 )