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Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies

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4 Author(s)
Moisiadis, Y. ; Integrated Syst. Dev., Athens, Greece ; Bouras, I. ; Papadas, C. ; Schoellkopf, J.P.

A low-voltage, high performance buffer suitable for implementation in standard CMOS technologies is proposed. The new buffer utilises the transient self back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 100 MHz and 0.9 V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer. With only 5% increase in power dissipation

Published in:

Electronics Letters  (Volume:35 ,  Issue: 2 )