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Self-checking of FPGA-based control units

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2 Author(s)
I. Levin ; Dept. of Comput. Sci., Tel Aviv Univ., Israel ; V. Sinelnikov

The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions. A self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. Comparison of code vectors being transferred between the blocks of the portions enables providing a totally self-checking property. The self-checking CU is implemented in a form of a one-rail network of interconnected pre-designed LUT-based configurable logical blocks. The self-checking checker is a Sum-Of-Minterms based checker. The proposed technique: a) does not require any encoding of output words; and b) uses one-rail design, thereby drastically decreasing the required overhead

Published in:

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Date of Conference:

4-6 Mar 1999