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Hierarchical scheduling in high level synthesis using resource sharing across nested loops

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3 Author(s)
Ghosh, A. ; Dept. of Electron. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA ; Lodha, S.K. ; Vemuri, R.

This paper presents a resource-constrained scheduling algorithm for hierarchical behavioral specifications containing nested loops. The algorithm attempts to share resources across levels, to schedule operations that belong to different levels of the nested loop structures in the specifications as well as operations that belong to the same level. We compare the results of scheduling using our algorithm with those obtained using traditional list scheduling with no sharing of resources among different levels of the specification. These results show an average improvement of 23.47% in terms of number of control steps

Published in:

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Date of Conference:

4-6 Mar 1999