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Self-checking synchronous controller design

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2 Author(s)
Kia, S.M. ; Dept. of Electr. & Comput. Eng., Queensland Univ., St. Lucia, Qld., Australia ; Parameswaran, S.

Efficient models are introduced for totally self-checking/code disjoint (TSC/CD) and strongly fault-secure/strongly code disjoint (SFS/SCD) synchronous controller models. These models are based on two low-cost, modular, TSC edge-triggered and error-propagating CD flip-flops. Properties of the proposed synchronous controller models are proven. The design procedure for these models and their proper applications are explained

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:146 ,  Issue: 1 )