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2.5 Gbit/s clock and data recovery circuit IC using novel duplicated PLL technique

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3 Author(s)
K. Kishine ; NTT Opt. Network Syst. Labs., Kanagawa ; K. Takiguchi ; H. Ichino

A 2.5 Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabricated using 0.5 μm Si bipolar technology. This CDR IC operates more stably in that it can tolerate greater variations in temperature and supply voltage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations

Published in:

Electronics Letters  (Volume:35 ,  Issue: 5 )