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Efficient simulation of MOS circuits

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2 Author(s)
R. Erwe ; Inst. fuer Theor. Elektrotech., Aachen, Germany ; N. Tanabe

Novel techniques are described which significantly speed up classical circuit simulation of MOS LSI circuits. By taking advantage of the unilateral properties of MOS transistors, modifications of Newton's method are developed, reducing the computational effort for the Gaussian elimination mainly for large circuits. Latency is another property of MOS circuits which can be exploited to enhance simulation efficiency. A latency exploitation technique is described. In contrast to methods published previously, no partitioning into subcircuits is required. These techniques can be easily implemented in circuit simulators

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:10 ,  Issue: 4 )