Referenced Items are not available for this document.
A new high performance bit parallel architecture for computing square roots is proposed. The architecture implements a non-restoring algorithm and is structured as a pipelined cellular array. To improve the performance, hybrid radix-2 adders are used. However, the conventional two's complement representation for both the radicand and square root is maintained
Published in:
Electronics Letters
(Volume:35
,
Issue:
3
)
Date of Publication: 4 Feb 1999
- Page(s):
- 185 - 186
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 6170489
- Digital Object Identifier :
- 10.1049/el:19990178
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 4 Feb 1999
- Sponsored by :
- Institution of Engineering and Technology
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