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Block implementation of a recursive least squares estimation algorithm

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3 Author(s)
Y. Iiguni ; Fac. of Eng., Kyoto Univ., Japan ; H. Sakai ; H. Tokumaru

A block implementation of a Schur-type algorithm for the recursive least-squares problem using parallel processors is described. The parallel architecture can simultaneously process block data in one hardware clock cycle with regularly and locally connected processing elements. Such a computing structure is desirable for VLSI implementation. Moreover, a latency penalty is on the order of the block size and the filter order, which is small as compared to the previous results

Published in:

IEEE Transactions on Acoustics, Speech, and Signal Processing  (Volume:36 ,  Issue: 10 )