Block implementation of a recursive least squares estimation algorithm

A block implementation of a Schur-type algorithm for the recursive least-squares problem using parallel processors is described. The parallel architecture can simultaneously process block data in one hardware clock cycle with regularly and locally connected processing elements. Such a computing structure is desirable for VLSI implementation. Moreover, a latency penalty is on the order of the block size and the filter order, which is small as compared to the previous results.<
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