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VLSI implementation of Tausworthe random number generator for parallel processing environment

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4 Author(s)
Saarinen, J. ; Dept. of Electr. Eng., Tampere Univ. of Technol., Finland ; Tomberg, J. ; Vehmanen, L. ; Kaski, K.

A fast Tausworthe-type random number generator has been implemented as a VLSI circuit on silicon for Monte-Carlo simulation purposes in a parallel multiprocessor system environment. The generator, which has uniform distribution, has been constructed for use as a peripheral device to be connected with each processor unit. General considerations for parallel random number generation are discussed and desirable properties are reviewed as a starting point for a VLSI implementation. The hardware design is based on the maximal length shift register sequences. It involves concurrent architecture in which a single shift operation is equivalent to 16 shifts in the original shift register unit. A new 16-bit random number is generated during each shifting operation. The chip is fully microprocessor bus compatible with a 16-bit bidirectional data bus and three I/O control lines. The methods of shift register sequence segmentation are also reviewed. Practical aspects for parallel processing system purposes are given. The generator has been submitted to a comprehensive set of statistical tests.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:138 ,  Issue: 3 )