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VLSI system compiler for digital signal processing: modularization and synchronization

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2 Author(s)
Ito, K. ; Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol, Japan ; Kunieda, H.

An overview of a VLSI system compiler that generates a highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms is described. The modularization and the synchronization of general digital signal processing algorithms in order to convert them into suitable forms for implementation by a processor array on a VLSI chip are described. Signal processing algorithms are modularized into the minimum number of inner-product modules by the proposed modularization procedure. Modularizing digital signal processing algorithms with low coefficient sensitivity parameters is also proposed. These modules are assigned to inner product processors. After processors have been placed and communication paths between them have been routed on a VLSI chip, the synchronization procedure derives a schedule for this VLSI system. The scheduling, which is free of both data conflict on interprocessor data links and inner-product operation execution conflict on processors, is investigated

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Circuits and Systems, IEEE Transactions on  (Volume:38 ,  Issue: 4 )