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High-speed, highly sensitive OEIC using clocked vertical BJT's photoDarlington in CMOS technology

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1 Author(s)
Ayadi, K. ; Semicond. Div., Siemens AG, Munich, Germany

A novel CMOS synchronized photoreceiver is proposed for conversion of optical input pulses to digital output signals. The photoreceiver circuit consists of a photoDarlington used as a detector of input light followed by a current-mirror comparator used as a converter to electronic signals. A combination of two p-n-p vertical CMOS bipolar junction transistors controlled by an external clock is designed to achieve the first clocked photoDarlington structure. The generated photocurrent is amplified and digitized by the current-mirror comparator in a return to-zero format. The synchronized photoreceiver has been implemented in a standard digital 0.7 μm, 5 V n-well CMOS technology with an effective area of 100×60 μm2. It was measured to operate at 100 MHz with an external input light of 13.3 fJ/pulse (-18.8 dBm/beam)

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 4 )