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An algorithm for determining repetitive patterns in very large IC layouts

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3 Author(s)
M. Niewczas ; Dept. of Electron., Warsaw Univ. of Technol., Poland ; W. Maly ; A. Strojwas

This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art IC's which suggest that the diversity of patterns does not significantly increase with increasing chip size

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:18 ,  Issue: 4 )