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A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols

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4 Author(s)
Heinrich, M. ; Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA ; Soundararajan, V. ; Hennessy, J. ; Gupta, A.

Scalable cache coherence protocols have become the key technology for creating moderate to large-scale shared-memory multiprocessors. Although the performance of such multiprocessors depends critically on the performance of the cache coherence protocol, little comparative performance data is available. Existing commercial implementations use a variety of different protocols, including bit-vector/coarse-vector protocols, SCI-based protocols, and COMA protocols. Using the programmable protocol processor of the Stanford FLASH multiprocessor, we provide a detailed, implementation-oriented evaluation of four popular cache coherence protocols. In addition to measurements of the characteristics of protocol execution (e.g., memory overhead, protocol execution time, and message count) and of overall performance, we examine the effects of scaling the processor count from 1 to 128 processors. Surprisingly, the optimal protocol changes for different applications and can change with processor count even within the same application. These results help identify the strengths of specific protocols and illustrate the benefits of providing flexibility in the choice of cache coherence protocol

Published in:

Computers, IEEE Transactions on  (Volume:48 ,  Issue: 2 )

Date of Publication:

Feb 1999

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