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Single-electron memory for giga-to-tera bit storage

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9 Author(s)
Yano, K. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Ishii, Tomoyuki ; Sano, T. ; Mine, T.
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Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures

Published in:

Proceedings of the IEEE  (Volume:87 ,  Issue: 4 )