Referenced Items are not available for this document.
Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures
Published in:
Proceedings of the IEEE
(Volume:87
,
Issue:
4
)
Date of Publication: Apr 1999
- Page(s):
- 633 - 651
- ISSN :
- 0018-9219
- INSPEC Accession Number:
- 6218923
- Digital Object Identifier :
- 10.1109/5.752519
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1999
- Sponsored by :
- IEEE
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