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SiO2 interface layer effects on microwave loss of high-resistivity CPW line

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5 Author(s)
Yunhong Wu ; Dept. of Electr. & Electron. Eng., Queen''s Univ., Belfast, UK ; Gamble, H.S. ; Armstrong, B.M. ; Fusco, V.F.
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For a coplanar waveguide (CPW) line where the metal conductor is in direct contact with the HR-Si substrate, the microwave losses are low but are sensitive to DC bias due to DC leakage current. With a continuous SiO2 layer inserted between the CPW metallization and HR-Si substrate, DC leakage is eliminated, but microwave losses increase. An MOS C-V analysis shows that an induced charge layer exists on the substrate surface and is the principle cause for increased line losses. If the insulated SiO2 layer beneath the conductor strips of line is made to be noncontinuous, then microwave losses are decreased from 18 to 3 dB/cm at 30 GHz

Published in:
Microwave and Guided Wave Letters, IEEE  (Volume:9 ,  Issue: 1 )

Date of Publication: Jan 1999

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