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During the design and re-engineering process, modeling the application's timing characteristics on the target architecture is necessary in order to evaluate the number of processors, communication fabric, and partitioning trade-offs required for an efficient design of a system. The over-all performance of most of COTS (commercial-off-the-shelf) systems, ranging from supercomputers to multiprocessor DSP (digital signal processing) systems, is uniquely affected by the behaviour of the communication primitives supported by them. To evaluate the performance of such systems, it is essential that temporal models, commonly known as performance models, reflect the effects of the communication primitives on the system performance. We propose a VHDL-based (VHSIC hardware description language) temporal modeling environment where we model the system's hardware as well as its accompanying software. We incorporated support for the message passing interface (MPI) standard into the modeling domain, allowing an architecture independent abstraction of application and more accurate model for communication primitives. This tool provides an excellent platform for temporal evaluation of systems under design and re-engineering. Finally, when coupled with code-generation tools, we are able to generate control software that can directly run on the target platform, simplifying the task of code design for legacy system upgrades.
Signals, Systems & Computers, 1998. Conference Record of the Thirty-Second Asilomar Conference on (Volume:2 )
Date of Conference: 1-4 Nov. 1998