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Architectural yield optimization for WSI

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2 Author(s)
Harden, J.C. ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; Stader, N.R., II

A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized

Published in:

Computers, IEEE Transactions on  (Volume:37 ,  Issue: 1 )