By Topic

Analysis and optimization of BiCMOS digital circuit structures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Embabi, S.H.K. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Bellaouar, A. ; Elmasry, M.I.

Circuit analyses and performance optimization are presented of three basic BiCMOS digital circuit structures: BiCMOS buffer, NMOS/CML (coupled-mode logic), and ECL (emitter-coupled logic)/CMOS interface circuits. The analytical modeling of the transient behavior offers insight into the critical circuit and device parameters that affect the performance of these circuits. Techniques to improve the speed of each structure and the tradeoff factors involved in designing such circuits are discussed. The derived delay expressions can also be used in CAD tools for optimizing BiCMOS circuits and systems

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 4 )