Referenced Items are not available for this document.
Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 μm BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:26
,
Issue:
4
)
Date of Publication: Apr 1991
- Page(s):
- 585 - 589
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 3920117
- Digital Object Identifier :
- 10.1109/4.75059
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1991
- Sponsored by :
- IEEE Solid-State Circuits Society
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