By Topic

100-MHz serial access architecture for 4-Mb field memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

A 4-Mb field memory with a 100-MHz serial access rate has been developed. A new architecture that significantly improves serial I/O operation speed, reduces layout area, and offers simple control is proposed. To accomplish this task, a new architectural data shifter and high-speed redundancy circuit have been developed. The field memory has a 568-line×960 pixel×8-b (4,362,240 b) memory cell array designed for high-definition television (HDTV) screens. A 1.0 μm CMOS process technology is used to produce a die size of 12.94 mm×25.9 mm. The write-read cycle time is 9 ns, the access time is 8 ns, and the active current is 170 mA at a 50-MHz cycle rate with a standby current of about 3 mA

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 4 )