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Fast-access BiCMOS SRAM architecture with a VSS generator

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4 Author(s)
Douseki, T. ; NTT LSI Lab., Kanagawa, Japan ; Ohmori, Y. ; Yoshino, H. ; Yamada, J.

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with VSS generator has been developed. Two key circuits, a VSS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 4 )