A CMOS power-delay model for CAD optimization tools

The need of fast and reliable models for CMOS gates has grown in importance not only for the simulation of digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also power consumption must be considered with increasing care. A simultaneous power-delay evaluation can be performed using a new model developed for sub-micron CMOS technologies, allowing better multi-objective optimization.