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A CMOS power-delay model for CAD optimization tools

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5 Author(s)
Delaurenti, M. ; Dipt. di Elettronica, Politecnico di Torino, Italy ; Masera, G. ; Piccinini, G. ; Roch, M.R.
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The need of fast and reliable models for CMOS gates has grown in importance not only for the simulation of digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also power consumption must be considered with increasing care. A simultaneous power-delay evaluation can be performed using a new model developed for sub-micron CMOS technologies, allowing better multi-objective optimization

Published in:

Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on

Date of Conference:

4-5 Mar 1999

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