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Design of reliable VLSI circuits using simulation techniques

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3 Author(s)
Hsu, W.-J. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Sheu, B.J. ; Gowda, S.M.

An iterative simulation method of predicting the impact of progressive device degradation on circuit performance due to common microelectronic failure mechanisms is described. Simulation schemes for the lifetime prediction of ASICs as well as modeling requirements for accurate and efficient simulation are presented. These simulation schemes have been implemented in the prototype reliability simulator RELY to evaluate circuit performance degradation and provide reliability enhancement information. Hot-carrier effects on submicrometer digital and analog circuits are used to demonstrate the approach. Experimental results on precharging circuitry for sense amplifiers and operational amplifiers are presented

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 3 )

Date of Publication:

Mar 1991

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