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A VLSI grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system

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4 Author(s)
Chen, D.C. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Yu, R. ; Rabaey, J. ; Brodersen, R.W.

The architecture and custom implementation of a grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system using hidden Markov models are described. The prototype has 3000, words and larger vocabularies and higher throughput can be obtained by adding more grammar processors. This subsystem contains two custom VLSI chips that perform the evaluation of starting word probabilities associated with the across-word transitions in the hidden-Markov-model (HMM)-based speech recognition system. This system has a maximum computation rate of 200 MOPS and an I/O bandwidth of 265 MB/s. All circuits were silicon compiled and were working on first silicon

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 3 )