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A 6-ns 256-kb BiCMOS TTL SRAM

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11 Author(s)

The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25°C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8-μm Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a ×8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm×10 mm

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 3 )

Date of Publication:

Mar 1991

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