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Memory system reliability improvement through associative cache redundancy

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3 Author(s)
Lucente, M.A. ; Mitre Corp., Bedford, MA, USA ; Harris, C.H. ; Muir, R.M.

The development of a VLSI device that provides memory system self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques is described. This device isolates hard errors in system memory by writing a true and complement pattern to each system memory location. Locations from an on-chip fully associative cache are then mapped into the address space in place of faulty locations. Since substitutions take place at the memory word level, this method is more efficient than page swapping. Access to the onchip cache occurs in parallel with access to system memory, so memory access time is not increased, as it is with error detection and correction (EDAC). Analysis shows that this device can extend the mission time of a nonredundant memory system by as much as 35 times

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 3 )