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A chip set for lossless image compression

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3 Author(s)
Shah, I.A. ; North American Philips Corp., Briarcliff Manor, NY, USA ; Akiwumi-Assani, O. ; Johnson, B.C.

The authors describe two chips which form the basis of a high-speed lossless image compression/decompression system. They present the transform and coding algorithms and the main architectural features of the chips and outline some performance specifications. Lossless compression can be achieved by a transformation process followed by entropy coding. The two application-specific integrated circuits (ASICs) perform S-transform image decomposition and the Lempel-Ziv (L-Z) type of entropy coding. The S-transform, besides decorrelating the image, provides a convenient method of hierarchical image decomposition. The data compressor/decompressor IC is a fast and efficient implementation of the L-Z algorithm. The chips can be used independently or together for image compression

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 3 )

Date of Publication:

Mar 1991

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