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Two-level pipelined systolic array graphics engine

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5 Author(s)
J. A. K. S. Jayasinghe ; Lab. for Network Theory, Twente Univ., Enschede, Netherlands ; F. M. El-Hadidy ; G. Karagiannis ; O. E. Herrmann
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The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-μm CMOS technology

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IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 3 )