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This digital fuzzy processor-designed and realized in 0.7-μm CMOS technology-demonstrates a processing rate from 80 to 320 ns. A parallel pipeline architecture supports fast selection of the active fuzzy rules. Specifically, we designed an Active-Rule-Selector for selecting a subset of the fuzzy rules, called active fuzzy rules, and divided the architecture into parallel and pipeline stages. Despite some initial difficulty, step by step our efforts yielded ever more feasible solutions. The foundry delivered the chip in 1997. So far, it works properly.