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Application of STD to latch-power estimation

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2 Author(s)
V. Zyuban ; Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA ; P. Kogge

In this paper, we use the recently developed static transition diagram technique to derive analytical formulas expressing latch power in terms of true and spurious switching activities at the data input. These formulas are verified through analog simulation and applied to a number of commonly used latch designs. The derived model will allow designers to substitute parameters of true and spurious switching activities into analytical formulas for quickly obtaining accurate latch power and then select latches which have the best power-dissipation characteristics for those parameter values.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:7 ,  Issue: 1 )