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Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits

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3 Author(s)
Abderrahman, A. ; Dept. de Genie Electr. et d''Inf., Ecole Polytech. de Montreal, Que., Canada ; Cerny, E. ; Kaminska, B.

We present an algorithm for automatically generating minimal test sets for parametric faults in linear analog circuits. In a previous work we elaborated a multifrequency test generation method (TPG) for such circuit faults. The method was formulated as a series of optimization problems that were solved by sequential quadratic programming (SQP) available in MATLAB. Such a standard optimization method processes local information and, consequently, cannot guarantee that the found solution is global. This may lead to a poor test selection. Furthermore, the method is semiautomatic and depends on various parameters that must be selected by an experienced user. In this paper, we propose a method based on constraint logic programming (CLP) using relational interval arithmetic (RIA) to solve these optimization problems as a series of constraint satisfaction problems (CSPs). The method is fully automatic and provides tight and guaranteed bounds on the true range of a multivariable nonlinear function. The correctness of the bounds stems from the enumeration of subdivisions of the function and its variable domains while discarding those subdivisions containing no solution. The tightness (i.e., the closeness to the true range) of the bounds can be refined to any desired degree by increasing the fineness of subdivisions imposed on the variable domains and the stringency of the termination criterion at the cost of an increased CPU time. The TPG method was implemented in CLP (BNR) prolog. The effectiveness of our approach is illustrated on a number of nonlinear functions known to be difficult, and two realistic electronic circuits in the context of TPG. Our algorithm accelerated the computation of the various parameters related to the test of a biquadratic filter by a factor ranging from 11 to 29 as compared to the Monte Carlo method

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:18 ,  Issue: 3 )

Date of Publication:

Mar 1999

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