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On the relation between bit delay for slot reuse and the number of address bits in the dual-bus configuration

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1 Author(s)
Sharon, O. ; Comput. Sci. Dept., Haifa Univ., Israel

In slotted, dual-bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, j>i, then the slot can be reused by a station k, k⩾j. We show that the necessary and sufficient length of addresses for full slot reuse is M-2 bits for w=0 and [(M-1)/2w-1 ]+w-2 bits for w⩾1 and M>1+2w, where w is the bit delay at every station

Published in:

Information Theory, IEEE Transactions on  (Volume:45 ,  Issue: 1 )

Date of Publication:

Jan 1999

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